I had the honor to present my paper “Beyond real number modeling: Comparison of analog modeling approaches.” at the “Forum on specification & Design Languages” (FDL) in Kiel. Thanks for the feedback I have got there and the perfect organisation
I had some health issues and was away from office quite some time. But now I am (partially) back, working through my backlogs and preparing for the FDL. Despite some final check-ups (and visiting some doctors) still to do, I
I am planning a new project called “COVER” – this stands for “CO-VER ification”, meaning to incorporate system level models and design for verification. It also stands for “COVER all angles” in a design flow to ensure first time right.
I created a stylesheet matching the actual CUAS powerpoint template as good as possible. You can download it including an example from the info drive (I:\EngIT\ISCD\Latex\cuastex_beamer.zip). –> best to be watched in fullscreen mode (usually <ctrl>-L or <strg>-L in most
Here another offer from Infineon. You can read a bit more about BAG here. You can find the contact address in the PDF as attached below for download:
Please check out the silicon austria labs web page for details how to apply. You can read a bit more about BAG here. Here the PDFs:
There is a master thesis work offered. See my post here, if you want to know what SystemC-AMS can do. Here is the PDF:
There will be a special session about SystemC-AMS on the next FDL (Forum on specification and Design Languages) in Kiel (September 15th to 17th, 2020).
After I got the BAG2 tutorial working, I decided to have a look at LAYGO, which is an alternate layout generator (the preferred layout generator in BAG2 is called XBase). Some designers at Infineon (industry partner in this project) mentioned
Thanks to Prof. Elad Alon, from BWRC, there is now BAG (to be more accurate: BAG2) support for the generic 45nm technology from Cadence available. I am really grateful for the support. I’ll incorporate this soon in our environment here