After I got the BAG2 tutorial working, I decided to have a look at LAYGO, which is an alternate layout generator (the preferred layout generator in BAG2 is called XBase). Some designers at Infineon (industry partner in this project) mentioned it might be better to use for non-finfet (planar, SOI) technologies. So I gave it a try. There is also some tutorial here.
I got the set up working and the first thing I tried was the “logic family generator” freely available by Berkeley for downlad. It generated a library with layout, schematics and symbols for the Cadence “fake” technology cds_ff_mpt in a swift – Hooray!