I am planning a new project called “COVER” – this stands for “CO-VER ification”, meaning to incorporate system level models and design for verification. It also stands for “COVER all angles” in a design flow to ensure first time right.
Infineon Austria master thesis offer (BAG)
Here another offer from Infineon. You can read a bit more about BAG here. You can find the contact address in the PDF as attached below for download:
SAL master thesis offers for several BAG topics
Please check out the silicon austria labs web page for details how to apply. You can read a bit more about BAG here. Here the PDFs:
After I got the BAG2 tutorial working, I decided to have a look at LAYGO, which is an alternate layout generator (the preferred layout generator in BAG2 is called XBase). Some designers at Infineon (industry partner in this project) mentioned
BAG and GPDK045 at CUAS – thanks Berkeley!
Thanks to Prof. Elad Alon, from BWRC, there is now BAG (to be more accurate: BAG2) support for the generic 45nm technology from Cadence available. I am really grateful for the support. I’ll incorporate this soon in our environment here
BAG repositories: sorting things out (download)
When I started with this topic, I was facing tons of repositories to dig through. So I made an attempt to sort things out a bit. I collected all repositories I found in two powerpoint slides, maybe it is some
Run BAG in the CUAS environment.
When I started in the ISCD group in March, one of my first tasks was to get BAG working. If you want to know what this is and how it works, you may want to look here or here. Meanwhile,