I am planning a new project called “COVER” – this stands for “CO-VER ification”, meaning to incorporate system level models and design for verification. It also stands for “COVER all angles” in a design flow to ensure first time right.
This project aims to connect system-level modeling using IEEE1666.1 (SystemC-AMS) with low-level modeling and design generation using BAG and Python.
It starts with two students, a third student will join next month, if everything works out. We also plan a publication of the results. A short overview can be found here: